1. Field of the Invention
The present invention relates to a voltage level shifting circuit, and in particular to an improved voltage level shifting circuit which is capable of increasing a level shifting speed and reducing a current consumption and a layout area.
2. Description of the Conventional Art
The conventional voltage level shifting circuit is disclosed in U.S. Pat. No. 4,845,381.
As shown in FIG. 1, the conventional voltage level shifting circuit includes a PMOS transistor 10 and a first inverter 11 which are connected in series between a Vpp terminal and a Vss terminal, and a PMOS transistor 12 and a second inverter 13 which are connected in series between the Vpp terminal and Vss terminal and connected in parallel with the PMOS transistor 10 and the first inverter 11.
The first inverter 11 includes a pull-up PMOS transistor PM1 and a pull-down NMOS transistor NM1 the gate of each of which receives an input signal Vin, and the first voltage terminal V1 is connected with the gate of the PMOS transistor 12.
The second inverter 13 includes a pull-up PMOS transistor PM2 and a pull-down NMOS transistor NM2 the gate of each of which receives an inverted input signal Vin, and the second voltage terminal V2 is connected with the gate of the PMOS transistor 10.
The operation of the conventional level shifting circuit will now be explained with reference to FIG. 1.
First, when a voltage Vss is inputted through the input terminal Vin, the voltage Vss is inputted into the first inverter 11, and a voltage Vdd is inputted into the second inverter 13.
Subsequently, the pull-up PMOS transistor PMI of the first inverter 11 and the pull-down NMOS transistor NM2 of the second inverter 13 are fully turned on, and the pull-up PMOS transistor PM2 of the second inverter 13 is slightly turned on.
Therefore, the driving capacity of the pull-down NMOS transistor NM2 is increased to a predetermined level which is higher than the driving capacity of the pull-down PMOS transistor PM2, the second voltage terminal V2 of the second inverter 13 becomes a voltage Vss, and the first voltage terminal V1 of the first inverter 11 becomes a voltage Vpp.
In addition, since the PMOS transistor 12 is turned off by the voltage Vpp of the first voltage terminal V1, the final output voltage Vout becomes a voltage Vss.
If a voltage Vdd which is lower than Vpp, is applied to the first inverter 11, and a signal corresponding to Vss is inputted into the second inverter 13, the pull-up PMOS transistor PM1 is slightly turned on, and the pull-down NMOS transistor NM1 is fully turned on, so that the driving capacity of the pull-down NMOS transistor NM1 is increased rather than the driving capacity of the pull-up PMOS transistor PM2.
Therefore, the voltage at the first voltage terminal V1 of the first inverter 11 becomes a voltage Vss, and the PMOS transistor 12 is turned on by the voltage Vss of the first inverter 11, whereby the voltage Vpp is applied to the second voltage terminal V2 of the second inverter 13.
At this time, the PMOS transistor 10 is turned off by the voltage Vpp of the second voltage terminal V2, so that the PMOS transistor 10 does not apply the power to the first voltage terminal V1.
Subsequently, the voltage at the first voltage terminal V1 of the first inverter 11 becomes a voltage Vss, and the PMOS transistor 12 is turned on by the voltage Vss, so that the output voltage Vout becomes a Vpp level.
Namely, the conventional voltage level shifting circuit receives a voltage Vdd and outputs a voltage Vpp (Vpp&gt;Vdd).
However, in the conventional voltage level shifting circuit, since the PMOS transistor 10 and the pull-up PMOS transistor PM1 each having a smaller driving capacity and the PMOS transistor 12 and the pull-up PMOS transistor PM2 are connected in series, the size (W/L: Width/Length) of the PMOS transistors should be increased in order to obtain a sufficient driving capacity.
Therefore, as the sizes of the PMOS transistors are increased, the layout area of the level shifter is disadvantageously increased.
In addition, since a level shifting from a low level to a high level is performed through the PMOS transistor 12 and the pull-up PMOS transistor PM2 each having a smaller driving capacity, it is impossible to obtain a fast level shifting speed.